In recent years, a multi-functionality of portable device typically portable telephones, has been realized, and a necessary capacity of a RAM (a random access memory) for realizing the multi-functionality tends to be increased. For this reason, there has been generated a new need to use the DRAM suitable for realizing the large capacity, in place of a past-used SRAM (static random access memory) which is characterized by a small consumption current. In case of using the DRAM, a refresh operation is necessary for allowing the DRAM to bold data, wherein a particular issue is to reduce a refresh current in a stand-by state.
The refresh current in the DRAM is decided depending on a time interval of the refresh operations to each cell of the memory cell array which constitutes the DRAM, or depending on a refresh cycle. As the refresh cycle is long, then the refresh current is small. This refresh cycle is decided depending upon a cell having a worst hold characteristic (a worst bit cell) in plural memory cells which constitute the memory cell array. The refresh cycle is adjusted to be shorter than a hold time of the worst bit cell, so as to allow the worst bit cell to hold data.
FIG. 1 is a diagram illustrative of a distribution of the number of cells versus the bold time of the memory cells in the DRAM. A horizontal axis of a graph shown in FIG. 1 represents the hold time, while a vertical axis represents the number of memory cells. In general, in al of the memory cells, the number of cells with good hold times is much lager than cells with bad hold times. Hold times of a majority of the cell tend to be better or longer by at least one digit than the hold time of the worst bit cell. However, the refresh cycle is decided by the hold time of the worst bit cell as shown in the figure. This means that a larger averaged current than a necessary averaged current is applied to the majority of the cells in the refresh operation.
One example of conventional techniques for reducing unnecessary refresh currents to the majority of the cells as shown in FIG. 1 is described in Japanese patent No. 2546161 (Japanese laid-open patent publication No. 6-89571). The semiconductor memory device described in this publication is as follows. A hold characteristic is measured by a probing test to the DRAM in the form of a wafer in the fabrication processes. Based on this measured hold characteristic and for each row address, a refresh operation is taken place to cells with bad characteristics at a normal refresh cycle, while another refresh operation is taken place to other cells at a longer refresh cycle than the normal refresh cycle. A control circuit is provided for performing the refresh operations. Switching the above two different refresh cycles is made by supplying an externally supplied refresh signal to the circuit for refresh operation directly or after the refresh cycle is elongated through a counter. Setting either signal to be used is made by a programming which is made by cutting wirings provided for each row address by utilizing a laser in the fabrication processes, or based on data read out for the operations for each row address, wherein the data corresponds to the hold data and have previously been stored in a programmable ROM (read only memory) for each row address.
Meanwhile, in the portable device integrating the above-described semiconductor memory device, a classification of the method of holding data to be stored in the semiconductor memory device may be, in case, made in accordance with an operational specification. In case of the portable telephone, for example, important data are first stored into a flash memory, so that the important data are holed or secured independent from whether the semiconductor memory device is in the stand-by state or not. For example, telephone number data are very important, for which reason the data are stored into the flash memory without storing the date into the RAM (non-volatile memory). Applications of the RAM are, for example, classified into two. First one is a work area for holding, in a short term, data which are temporary used in a variety of processings of CPU (central processing unit). The CPU has a memory which has, however, an extremely small capacity. For this reason, it is necessary to use a partial area of the RAM. The remaining area thereof is used for storing data for a long term. In the stand-by state of the portable telephone, less external information is entered therein, but the CPU may, in case, process when user does not use the portable phone. For example, a calculation of fee or a communication to a base station may be made. Data to be used for those processes are stored in the memory area for the long term store, without causing the data to be disappeared in the stand-by state. If values of data remain unchanged during the stand-by state, then it may be considered to store the data into the flash memory. In the processes, it is preferable to store data into the RAM because an access to the flash memory is slow and takes much times.
Examples of conventional techniques for reducing the consumption current of the DRAM in the stand-by state in consideration of the above-described conditions in use of the device are described in Japanese laid-open patent publications Nos. 11-213658 and 2000-21162. In the semiconductor devices described in those publications, the memory cell array is divided into a plurality of areas, so that only a part of the memory cell array is refreshed without refreshing the entirety of the memory cell array. The memory cell array is divided into some memory areas, so that, for example, in two memory areas, only a memory area storing important informations is refreshed, and another memory area storing non-important informations is not refreshed. A value of RCB (refresh control bit) is externally designated in order to allow setting an area to be refreshed in the memory cell area.
In the conventional techniques described above, the refresh cycle may be switched for each row address in consideration of the hold characteristic. In this case, the increase in the memory capacity of the DRAM causes increase in scale of a switching circuit or a circuit for holding the data for the switch, and takes a longer time for read out the data, and further increases the consumption current for operating those circuits.
On the other hands, in accordance with the techniques described in Japanese laid-open patent publications Nos. 11-213658 and 2000-21162, the operation mode of the memory device is adopted for an operation mode of the device integrating the memory device without, however, taking into account the hold characteristic of the memory cells.